Zhenxing Hu

Zhenxing Hu is a Senior Signal Integrity Engineer and Project Leader at 华为 since July 2005, with expertise in signal integrity analysis, PCB design, PCB cost management, interconnect project management, and ASIC co-design. Zhenxing also worked as a High-Speed Interface and Packaging SI Engineer at Hisilicon for a brief period in June 2020. Zhenxing holds a Bachelor's degree in Electronic Information Engineering from Beihang University, obtained between 2001 and 2005.