Jared Bold

Jared Bold is an experienced engineer with a strong background in verification and embedded development, currently serving as an FPGA Verification Engineer at Hudson River Trading since December 2020. Previously, Jared held the position of Verification Engineer at IBM, where responsibilities included developing a C++ verification environment for POWER processors, debugging verification software, and designing a continuous integration platform. Early career experience includes an internship at HCL America focused on embedded software development for image processing and a co-op at RailComm developing firmware for rail technologies. Jared holds both a Master of Science and Bachelor of Science in Electrical and Electronics Engineering from the Rochester Institute of Technology.