Bart De Vuyst

Bart De Vuyst is a Principal Analog Design Engineer at ICsense Ghent, where they specialize in A/D and D/A conversion, and possess extensive design knowledge of various analog building blocks. They previously served as a Specialist Analog Design at SOFICS from 2019 to 2023 and earned a PhD in Electrical and Electronics Engineering from Ghent University from 2007 to 2015. Prior to their current role, Bart held various positions at ICsense, including Senior Design Engineer and Project Manager, overseeing multiple mixed-signal ASIC design projects. They began their career as a PhD student researching continuous-time sigma-delta modulators at Ghent University and worked as an intern at Gemidis, designing an automated test structure for measuring wire bonds.