Yassine Fadel

Yassine Fadel is an ASIC Design Verification Trainee at indie Semiconductor since March 2023, where duties involve verifying the design of an active project with the verification team, focusing on directed tests at the SoC-level. Previously, Yassine completed an FPGA Design Verification Intern position at Safran Engineering Services in February 2023, devising an optimized FPGA design simulation environment utilizing the Python library CoCoTB. In July 2022, Yassine interned at SADA Robotics, developing new wireless programming techniques for ESP32 microcontrollers, specifically creating a Wireless Firmware Updater. Yassine holds an Engineer's degree in Embedded Systems and Digital Services from Institut National des Postes et Télécommunications, attained in September 2023, and completed CPGE classes with a focus on PCSI-PSI before that.