Harsh Naik

Harsh Naik is a Lead Principal Engineer at Infineon Technologies, specializing in silicon and GaN power semiconductor design since August 2013. Prior experience includes a summer internship at Power Integrations focused on characterizing and modeling device mismatch in analog circuits and performing device simulations for high voltage MOSFETs, as well as a summer internship at Alpha & Omega Semiconductor where capabilities were developed in calibrating Sentaurus test benches for MOSFET simulations and designing novel silicon diodes. Early career experiences include a summer internship at the University of Western Australia, working on the characterization of mercury cadmium telluride superlattice photodetectors. Harsh Naik holds a PhD in Electrical and Electronics Engineering and a Master’s degree from Rensselaer Polytechnic Institute, along with a Bachelor’s degree in Electrical Engineering from the Indian Institute of Technology, Madras.