Sushant Kumar

Sushant Kumar is an accomplished Design Verification Engineer with 7 years of experience in VLSI design and verification, specializing in advanced digital methodologies. They are proficient in scripting languages such as Perl, Python, and MATLAB, and have a strong foundation in VHDL, Verilog, System Verilog, and UVM. Sushant has a demonstrated expertise in developing testbenches, creating test cases, and performing coverage analysis to ensure efficient designs, with experience working on various bus protocols. Currently, Sushant is enhancing their skills through a Certificate Program in Digital VLSI Design from IIT Delhi.