Thomas Jones

Thomas Jones is a seasoned digital design engineer with extensive experience in ASIC design and system architecture. Currently serving as a Digital Design Principle Engineer at INNOPHASE, Thomas has architected a multiprocessor compute subsystem for a 5G ORAN chip and mentored junior engineers. Previous roles include Principal ASIC Design at Groq, where Thomas created conversion functions for architectural exploration, and Senior Principal Design Engineer at Cadence Design Systems, focusing on chip sets for the Palladium Emulation Platform. Thomas's background features significant contributions at NVXL Technology, Enphase Energy, Echelon, TiMetra/Alcatel, Sebring/PLX Technology, Aspect Telecommunications, and Amdahl, showcasing expertise in high-performance computing and advanced design methodologies. Educational qualifications include an MS in Computer Engineering from Santa Clara University and a BS in Computer Systems Engineering Technology from Oregon Institute of Technology.