Anupama Agashe

Anupama Agashe is an experienced engineering professional currently serving as an Engineering Manager in SV Validation at Intel Technologies India since January 2017. Prior to this role, Anupama worked as a Design Engineer at Intel Technology India (P) Ltd, focusing on graphics domain RTL coding and design for debugability. Anupama's earlier experience includes positions as a Senior Design Engineer at LSI Research India, where responsibilities included DFT and transition delay fault pattern generation, and as a Consultant and Corporate Trainer at Sandeepani-CoreEL Technology, overseeing FPGA projects and conducting training on Verilog and VHDL. Anupama's career began at Texas Instruments India Ltd. working on ADSL router devices, and at CG-CoreEL Logic Systems, focusing on high-speed networking technologies. Anupama holds a Bachelor of Engineering degree in Electronics from Savitribai Phule Pune University and Vishwakarma Institute of Technology.