Viren Bansal

Viren Bansal is an Engineering Manager at Intel Corporation, bringing 20 years of experience in ASIC Design and Verification. They have expertise in front-end activities including RTL development, integration, design verification, and timing closure for multi-million gate chip execution. Prior roles include Senior Staff Engineer at Qualcomm, Sr. Principal Engineer at Broadcom Limited, and Principal Lead at Texas Instruments. Viren completed a BE in Electronic and Telecom from the College of Engineering, Pune, and a Diploma in VLSI from CDAC, Pune.