Eric Lee

Eric Lee is a seasoned engineering professional with extensive experience in the semiconductor industry, currently serving as a Process Engineering Manager at STATS ChipPAC since 2006. Eric's expertise includes various processes such as wafer backgrind, dicing, and die attach, and Eric is skilled in training Six Sigma, SAS JMP, FMEA, and 8D methodologies. Prior to STATS ChipPAC, Eric worked as a Staff Process Engineer at National Semiconductor, focusing on new package development and mold compound development, and as a Process Engineer at NEC Semiconductors Singapore, specializing in wire bond and molding processes. Eric holds a Bachelor of Engineering in Mechanical Engineering from the National University of Singapore.