JCET Group
Eric Lee is a seasoned engineering professional with extensive experience in the semiconductor industry, currently serving as a Process Engineering Manager at STATS ChipPAC since 2006. Eric's expertise includes various processes such as wafer backgrind, dicing, and die attach, and Eric is skilled in training Six Sigma, SAS JMP, FMEA, and 8D methodologies. Prior to STATS ChipPAC, Eric worked as a Staff Process Engineer at National Semiconductor, focusing on new package development and mold compound development, and as a Process Engineer at NEC Semiconductors Singapore, specializing in wire bond and molding processes. Eric holds a Bachelor of Engineering in Mechanical Engineering from the National University of Singapore.
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JCET Group
JCET Group is the world’s leading integrated-circuit manufacturing and technology services provider, offering a full range of turnkey services that include semiconductor package integration design and characterization, R&D, wafer probe, wafer bumping, package assembly, final test and drop shipment to vendors around the world. Our comprehensive portfolio covers a wide spectrum of semiconductor applications such as mobile, communication, compute, consumer, automotive, and industrial, through advanced wafer-level packaging, 2.5D/3D, System-in-Package, and reliable flip chip and wire bonding technologies. JCET Group has two R&D centers in China and Korea, six manufacturing locations in China, Korea, and Singapore, and sales centers around the world, providing close technology collaboration and efficient supply-chain manufacturing to our global customers.