Steven Loi

Steven Loi has extensive experience in the field of engineering, specifically in the areas of FPGA and ASIC design. Steven has held various roles throughout their career, starting with their current position as a Staff FPGA Design Engineer at Kateeva since January 2021. Prior to this, they were an ASIC Design Engineer at Microsoft from March 2020 to December 2020. Steven also worked at Kateeva previously, where they held the role of Staff FPGA Design Engineer from January 2017 to January 2020. Before that, they worked as a Senior FPGA Hardware Engineer at EFI from April 2013 to January 2017. Steven also gained valuable experience at Sigma Designs as a Staff Engineer from March 2007 to February 2013. Prior to that, they served as an ASIC Designer at NuCORE Technology from November 1999 to March 2007. Steven's early career includes roles as an ASIC Designer at Silicon Magic from November 1996 to November 1999, as well as at Cornerstone Imaging from October 1995 to November 1996. Steven began their professional journey as an ASIC Designer at Oki Semiconductor America from August 1993 to October 1995. With over 20 years of experience in the field, Steven Loi has a strong foundation in FPGA and ASIC design.

Steven Loi attended California State University-Sacramento where they pursued a Bachelor of Science degree in Electrical Engineering. The start and end years of their education are not provided.