Robert Lanier

Robert Lanier is a Lead FPGA Engineer with L3Harris Technologies, boasting over 20 years of experience in FPGA and ASIC design. Previously, they served as a Verification Engineer at NASA Jet Propulsion Laboratory and a Senior ASIC Design Engineer at Atmel Corporation, where they contributed to the development of various digital logic components. Robert has extensive expertise in UVM verification, SystemVerilog, and hardware architecture, making them a strong engineering professional in the field. They studied at the University of Central Florida from 1992 to 1994.