Aswin Patel is a Design Verification Engineer currently employed as a Senior Staff Engineer at Marvell Technology, focusing on DDR protocol and memory controllers. With extensive experience in the semiconductor industry, they have held various roles at Cadence Design Systems, including Principal and Lead Design Engineer, where they specialized in DDR Controller Design Verification. Aswin also worked as a Senior Engineer at Mindtree, collaborating with Texas Instruments and Intel Corp. They earned a Master of Technology focused in MicroElectronics from the Birla Institute of Technology and Science, Pilani.
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