Chethan T Bhat

Chethan T Bhat is a Senior ASIC Design Engineer at Marvell Technology, having transitioned from the position of ASIC Design Intern at the same company in November 2023. With prior experience as an ASIC Design and Verification Trainee at Maven Silicon and an FPGA Design Intern at e-Yantra, IIT Bombay, Chethan has developed a strong foundation in ASIC design and embedded systems. Chethan holds a Master of Science in Computer Engineering from North Carolina State University, completed in December 2023, and a Bachelor of Engineering in Electrical, Electronics and Communications Engineering from RN Shetty Institute of Technology, awarded in 2021.