Clayton Shen

Clayton Shen is a seasoned engineering professional with extensive experience in Design for Test (DFT) across various semiconductor companies. Currently serving as a Senior Principal DFT Engineer at Marvell Semiconductor since February 2019, Clayton specializes in DFT design, verification, and post-silicon validation for complex System on Chip (SoC) and demodulator chips. Previous roles include Lead DFT Engineer at Netronome and Senior Hardware Engineer at Availink, where responsibilities encompassed establishing and maintaining DFT flows for scan, embedded built-in self-test (MBIST), analog IP testing, and high-speed interface testing. Early career experience as an ASIC designer at Spreadtrum involved the integration of SOC components, verification of video decoders, and DFT for SOC chips. Clayton holds a Master's degree in Electronic Engineering and a Bachelor's degree in Electronics Engineering, both from Peking University.