Harry Yang

Harry Yang is an experienced Principal Verification Engineer at Marvell Technology since July 2022, specializing in DSP verification for Ethernet PHY. Prior to this role, Harry served as a Senior Staff ASIC Verification Engineer at Xilinx, focusing on ethernet and interlaken IP group from January 2014 to July 2022. Harry's career includes positions as Senior ASIC Verification Engineer at IDT, where RapidIO protocol ASIC verification was conducted, and as an ASIC verification consultant at Diablo Technologies, involving DIMM register ASIC verification and associated tasks. Additional experience encompasses verification roles at Neterion and Nortel, where work included 10G ethernet adapter ASIC verification and FPGA verification for Enhanced CDMA base station controllers, respectively. Academic qualifications include an M.Eng in Electronics Engineering from Carleton University and a B.Eng in Microelectronics from Tsinghua University.