Jing Bai

Jing Bai is a Principal Physical Design Engineer at Marvell Semiconductor, specializing in back-end design for advanced tech nodes. They have a strong foundation in IC design flow methodology, having previously held positions at companies like Broadcom and Intel, where they focused on power optimization, timing analysis, and place and route. Jing began their career as an ASIC design engineer intern at Semiconductor Manufacturing International Corporation, then progressed to roles including Logic CAD Engineer II at NetLogic Microsystems. Jing holds a Master’s degree in Electrical Engineering from the University of Southern California and is currently pursuing a Bachelor’s degree at Beijing University of Technology.