Mandar Patil is a Senior Principal Engineer at Marvell Technology, where they have been employed since 2018 and currently contribute to ASIC design verification and validation. With over 20 years of experience, they specialize in test-plan generation, test-bench development in SystemVerilog using UVM methodology, and have a strong knowledge of Ethernet protocols. Mandar's career includes roles as an ASIC Design Engineer at ControlNet India Pvt Ltd and as a Senior Verification Engineer at Centillium Communications. They also served as a Principal Verification Engineer at Infinera from 2008 to 2018. Mandar earned a B.Tech in Electronics and Telecommunication from Dr. Babasaheb Ambedkar Technological University and a diploma in Engineering from Swami Vivekanand Education Polytechnic.
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