Sadhvi Varagur Karthikeyan

Sadhvi Varagur Karthikeyan is a Staff Digital Design Engineer at Marvell Technology since December 2023, with prior roles including Sr ASIC Design Engineer at Qualcomm from September 2021 to December 2023, FPGA Engineer at Achronix Semiconductor Corporation from August 2020 to August 2021, and Senior Digital Design Engineer, Digital Design Engineer, and Graduate Digital Design Engineer at Dialog Semiconductor from July 2016 to August 2020. Sadhvi's early experience includes a Digital Design Internship at Dialog Semiconductor in late 2015 and a Research Internship at Universitat Politècnica de Catalunya, where work involved designing an FPGA-based Optical Communication Link. Educational qualifications include a Master's degree in Electrical and Computer Engineering from the University of Florida (2014-2016) and a Bachelor of Technology in Electrical, Electronics, and Communications Engineering from Shanmugha Arts, Science, Technology and Research Academy (2010-2014).