Swati Chavan

Swati Chavan is a Senior Staff Engineer at Marvell Technology, with a career spanning over a decade in the semiconductor industry. Since October 2021, Swati has contributed to PNR flow on 16nm technology and gained hands-on experience with Cadence Encounter. Prior positions include Staff Engineer at Marvell Technology, MTS at Innovium Inc., and SOC Design Engineer at Intel Corporation. Swati began the career as an ASIC Engineer at eInfochips and undertook an internship as an ASIC Design Engineer at IIVDT. Academic qualifications include a Master’s degree in VLSI Technology from North Maharashtra University and a Bachelor’s degree in Electronics and Telecommunication from MITCOE, Pune.