Ashish Hegde

Ashish Hegde has over 19 years of experience in the semiconductor industry, currently serving as a Manager and Senior ASIC Designer at NVIDIA since April 2008. Responsibilities include SOC/full-chip and unit level verification utilizing SystemVerilog (VMM, UVM) and C++, as well as silicon bringup and ASIC prototyping/emulation with FPGA. Prior to NVIDIA, Ashish worked as a Design Engineer at Sasken, focusing on unit level verification and RTL coding, and as a Software Engineer at LnT Infotech, where coding device drivers was the primary responsibility. Ashish began the professional journey as an intern at Zeta Infotech Pvt Ltd, developing Verilog and SystemVerilog test cases. Ashish holds a Bachelor's degree in Electronics and Communications Engineering from Manipal Institute of Technology, complemented by a pre-university education in Physical Sciences and an SSLC from Manipal Academy of Higher Education.