Debdut Biswas is an accomplished Analog RF VLSI designer with a robust academic background. They earned a Bachelor of Technology from West Bengal University of Technology in 2010, followed by a Master of Technology in 2013 and a Doctor of Philosophy from the Indian Institute of Technology, Kharagpur, in 2020. Debdut has served as a Lead Design Engineer at Cadence Design Systems from 2020 to 2022 and is currently a Staff Engineer at MediaTek since 2022. Prior to these roles, Debdut was a Member Technical Staff at Terminus Circuits Pvt Ltd from 2019 to 2020.
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