Trong Nguyen

Trong Nguyen is a skilled Physical Design Engineer with extensive experience in the semiconductor industry. Since March 2020, Trong has been working at MediaTek, having previously held similar roles at Marvell Semiconductor from October 2018 to March 2020 and at Renesas Design Vietnam Co., Ltd from September 2015 to October 2018. Expertise includes designing full flow IP at 16nm and lower, with responsibilities encompassing floor-planning, clock tree synthesis (CTS), place and route (P&R), timing optimization, static timing analysis (STA), physical verification, and timing debugging. Trong holds a Bachelor's degree in Computer Engineering from the University of Information Technology, earned in 2015.