Chaitanya M

ASIC Design Engineer -1-physical Design At Signoff Semiconducters at SignOff Semiconductors

Chaitanya M has a strong background in electrical and electronics engineering, with experience in various roles such as ASIC Design Engineer, Engineer for Servicing Testing & Commissioning, Solar Power Plant Operations and Maintenance Engineer, and Embedded Technical Trainer. Currently working as an ASIC Design Engineer at SignOff Semiconductors, Chaitanya M has gained valuable hands-on experience and knowledge in the field. Chaitanya M holds a Master's degree in Power Electronics and has a proven track record of maintaining good relationships with clients and implementing innovative ideas.

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Timeline

  • ASIC Design Engineer -1-physical Design At Signoff Semiconducters

    February, 2023 - present

  • Physical Design Engineer Trainee At Signoff Semiconducters

    July, 2022

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