Yu-Sheng Wu has extensive experience in the semiconductor industry, serving as an Integration Engineer at TSMC from February 2017 to May 2024, focusing on logic-based BCD technology development, managing project items, and collaborating with various teams on HV LDMOS analysis and design rules. In the role of Device Engineer, contributions included high-k/MG process device performance analysis and optimization, resulting in conference papers and a US patent. Currently, Yu-Sheng Wu is a Technical Manager at 聯發科技, overseeing power management IC tapeout and manufacturing since February 2021. Yu-Sheng Wu holds a Ph.D. in Semiconductor Device Modeling and Simulation from National Chiao Tung University, where studies were completed between 2006 and 2011, after obtaining a Master's Degree in the same field from the same institution in 2006.
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