Hajime (Jim) Terazawa

Hajime (Jim) Terazawa has over 40 years of experience in the semiconductor industry. Hajime (Jim) began their career in 1978 as a Design Engineer at Texas Instruments. In this role, they contributed to reducing the Cycle Time by establishing a methodology for automatically extracting and installing OPC features and SRAF generated by the RET Team into the complete cell arrays. Additionally, they were the design lead for the 512K and the 2Meg SRAM designs for the statistical defect analysis (SDA) purposes. In 2008, Terazawa joined PDF Solutions as a Senior Design Engineer and Technical Consultant. In this role, they successfully generated SRAM cell-based test structures for test chips at 45nm, 40nm, and 32nm CMOS and SOI processes to detect systematic failures and misalignment sensitivities of certain layers that could affect production ramp-up and yield improvement. In 2013, they joined GLOBALFOUNDRIES as an MTS Design Engineer. Finally, in 2018, they joined Menlo Micro as a Senior Layout Engineer.

Hajime (Jim) Terazawa has a Bachelor's degree in Electrical Engineering from Michigan Technological University and a Bachelor's degree in Electronics Engineering from Tamagawa University.