Bhuvan Challa is an experienced engineer specializing in ASIC design and analog/mixed signal engineering. Bhuvan began a career at Cadence Design Systems as a consultant and intern before advancing to Synopsys Inc, where Bhuvan held roles as an Analog and Mixed Signal Design Engineer at two levels. Subsequently, Bhuvan joined AMD as a Member of Technical Staff in SIPI CAD, continuing until June 2025, and is currently employed at Meta as an ASIC Engineer in Infra Silicon. Bhuvan holds a Bachelor of Technology in Electrical, Electronics and Communications Engineering from Jawaharlal Nehru Technological University and a Master of Engineering in Electrical Engineering from the University of Cincinnati.
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