Pallavi S. has extensive experience in the engineering field, with a career spanning over two decades. Starting as an ASIC Design Engineer at Paxonet Communications from 2000 to 2003, Pallavi advanced to the role of Senior ASIC Design Engineer at Cisco Systems, contributing from October 2006 to March 2017. Following a brief tenure as a Hardware Engineer at Barefoot Networks from April 2017 to November 2017, Pallavi joined Meta, currently serving in the capacity of AI/HPC Systems.
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