Pavani Banoth

Pavani Banoth is a seasoned VLSI engineer with extensive experience in physical design and implementation across multiple prestigious companies. At Wipro, Pavani contributed to tape-outs involving designs of up to 0.5 million gates for 14 nm technology. Subsequent roles included a senior position at Cerium Systems, focusing on tape-outs for designs up to 2 million gates at 7 nm, where significant contributions were made to RTL to GDS implementation. Pavani also served at Synopsys Inc as a Staff Engineer, integrating MS-CTS scripts to enhance customer workflows. More recently, positions at Meta involved RTL to netlist implementation on advanced 3 nm technology, culminating in expertise in both block-level physical implementation and critical floorplanning strategies at Whizchip Design Technologies Pvt Ltd.