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ASIC Design Engineer

Weiwei Jiang is an experienced Senior Research and Development Engineer currently working as an ASIC Design Engineer at Meta. With a robust background in the computer software industry, they have previously held positions as a researcher at Tsinghua University and as a co-op engineer at AMD. Weiwei also served as a Senior R&D Engineer at Synopsys Inc and a Senior Silicon Generalist at Google, specializing in FPGA prototyping, ASIC chip design, and algorithm development. They hold a Doctor of Philosophy in Computer Science from Columbia University, where they also earned a Master's degree in the same field and a Bachelor's degree in Electrical Engineering from Tsinghua University.

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Sunnyvale, United States

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