Sandeep Radhakrishnan is an experienced engineer currently working as a Hardware Design Engineer at Meta since August 2022, following a tenure as a Silicon Architecture Engineer at Intel Corporation from March 2021 to August 2022. With initial experience as a Design Engineer at CG CoreEl from October 2009 to June 2012 and a Senior Digital Design Engineer at Cirrus Logic from February 2014 to March 2021, Sandeep has accumulated over three years of expertise in FPGA-based RTL design, as well as substantial knowledge of video compression standards, particularly MPEG4 Part 10 (H.264). Educational qualifications include a Master of Science in Computer Engineering from North Carolina State University (2012-2013) and a B.Tech in Electronics and Communication from Amrita School of Engineering (2005-2009). Additionally, Sandeep completed a certification course on FPGA-based RTL design, verification, and validation through Xilinx.
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