Sarath Racherla

Sarath Racherla is an experienced engineer specializing in ASIC verification and RTL design. Currently serving as a Member of Technical Staff - Silicon at Fungible, Inc. since April 2017, Racherla focuses on RTL Design and ASIC Verification using SystemVerilog and UVM. Previous roles include ASIC Engineer at Juniper Networks, where Racherla worked on verification of packet processing blocks and developed functional reference models in SystemC. At STEC Inc, Racherla received an excellence award for contributions to the CellCare project in NAND flash technology. Earlier experience includes positions at Mentor Graphics, Qualcomm, and Cognizant Technology Solutions. Sarath holds a Master’s degree in Electrical Engineering from North Carolina State University and a Bachelor’s degree in Electronics and Communications Engineering from Chaithanya Bharathi Institute of Technology.