SP

Sayaji P.

Design Verification Engineer at Meta

Sayaji P. is an experienced engineering professional with a strong background in design verification and machine learning, currently serving as a Design Verification Engineer at Meta since April 2022 while also working as a Machine Learning Engineer at a stealth startup since August 2020. Previous roles include staff engineer at Intel Corporation, design verification engineer at Facebook, and ASIC verification engineer at Tachyum, among others. Sayaji P. has accumulated experience across various leading technology companies, including Microsoft, Google, and Danaher Corporation, focusing on areas such as ASIC, FPGA, and SoC verification. Sayaji P. holds a Master of Science in Electrical and Computer Engineering from the Georgia Institute of Technology.

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