Venkatesh Satrawada is a skilled engineer with extensive experience in ASIC digital design. Venkatesh began as a design engineer intern at Esencia Technologies Inc. and progressed to consulting roles at Texas Instruments, LSI Logic/Agere Systems, and Meta. Holding the title of Senior ASIC Digital Design Engineer at Meta since March 2021, Venkatesh previously served as an ASIC Digital Design Engineer from April 2018 to March 2021. Venkatesh earned a Bachelor of Engineering degree from Visvesvaraya Technological University and a Master of Science degree from UCLA.
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