Seshanna Katam

Seshanna Katam is an experienced ASIC Physical Design Engineer with over three years in the field. Currently, they work at Intel India Technologies Pvt Ltd., having previously held positions at Micron Technology and Intel Corporation, where they contributed to SOC design and block-level netlist to GDS processes. Seshanna holds an MS by Research in Electrical, Electronics, and Communications Engineering from the National Institute of Technology, Tiruchirappalli, and a Bachelor of Technology from Jawaharlal Nehru Technological University. Their expertise includes physical synthesis, timing closure, and EDA tools such as Synopsys and Cadence.