Harshitha D is a Senior ASIC Physical Design Engineer currently at Synopsys Inc, with extensive experience in netlist to GDS processes and design enclosure, primarily utilizing Synopsys tools. They have previously worked at Wipro and Chip Edge Technologies, contributing to multiple technology nodes, including advanced 3nm and 4nm processes. Harshitha holds a Master of Technology in Electrical and Electronics Engineering from the Birla Institute of Technology and Science, Pilani, and a Bachelor of Engineering in Electrical, Electronics, and Communications Engineering from RNS Institute of Technology.
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