Eshaan Agarwal

Eshaan Agarwal is a highly motivated Design Verification Engineer with extensive experience in RTL coding, synthesis, and verification using Verilog, SystemVerilog, and C++. Eshaan has worked at notable companies such as Qualcomm, Juniper Networks, and Microsoft, currently serving as a Senior Design Verification Engineer. Prior to this, Eshaan completed internships at Lam Research, Broadcom, and Parimics, focusing on firmware development and automation. Eshaan holds a Master’s degree in Electrical Engineering from San Jose State University and a Bachelor’s degree in Electronics and Communication from Panjab University, along with additional training in verification from the University of California, Santa Cruz.