Juhi Pandey

Juhi Pandey is a Senior RTL Engineer at MicroVision since July 2018, specializing in RTL design, IP integration, verification, and hardware debug for automotive lidar applications using Verilog/System Verilog on Zynq Ultrascale+ FPGA. Previous experience includes an Electrical Engineer Intern role at Airbus Group, where Juhi worked on a master thesis involving the modeling and prototype implementation of a solar power generator for a microsatellite, as well as an internship focusing on the design and development of a digital interface module. Juhi also served as an Executive Engineer at Siemens, engaged in the design of control and monitoring systems for metro rail projects, and completed an industrial internship at Alstom involving a 220kV conversion substation. Academic qualifications include a Master of Science in Power Engineering from Fachhochschule Darmstadt and further studies in Embedded and Real-time systems programming at the University of Washington, alongside a Bachelor's degree in Electrical and Electronics Engineering from Guru Gobind Singh Indraprastha University.