Jing-Chyi Liao

Jing-Chyi Liao is a seasoned engineer with a Ph.D. in Electrical Engineering from National Cheng Kung University. Currently serving as a Principal Engineer at MStar Semiconductor since April 2012, Jing-Chyi Liao specializes in foundry model QA, new model construction, device and chip-level reliability consulting, and IO circuit design. Prior experience includes a tenure at TSMC from 2009 to April 2012, where Jing-Chyi Liao conducted SRAM device analysis and process improvement as well as SRAM cell-level simulation. Additionally, a role as a Senior Engineer at AUO in early 2009 involved setting up reliability and electric test equipment and studying reliability mechanisms of TFT devices.