Yosi Arbeli

Yosi Arbeli is a VLSI Front End Tech Lead at NextSilicon since March 2025. Previously, Yosi Arbeli worked at Mobileye from December 2006 to March 2025, specializing in ASIC Logic Design with a focus on the design of high-speed, low-power VLIW-SIMD and RISC processors, alongside large arithmetic units, high-capacity MAC machines, and advanced memory access controllers. Prior to that, Yosi Arbeli served as a teaching assistant for VLSI devices and systems as well as a microcontrollers lab mentor at Jerusalem College of Engineering from September 2005 to April 2007. Yosi Arbeli holds a Bachelor of Science degree in Electronics Engineering from Jerusalem College of Engineering, earned between 2002 and 2006.