Marco Alejandro Castellon

Marco Alejandro Castellon is a Senior Digital Hardware Engineer at NovAtel Inc. since May 2006, specializing in system-level requirements, architecture definition, FPGA, and ASIC design. Prior experience includes roles as a Hardware Engineer at Acceleware, developing FPGA-based accelerators for cryptography algorithms, and at CSI Wireless, focusing on GPS receiver digital design and PCB design, where specifications and test plans were developed. Previously, Castellon worked as a Hardware Developer at Wind River, creating reference designs for consumer internet appliances, and as a Hardware Engineer at AudeSi Technologies Inc., where responsibilities included digital embedded hardware designs for SmartCards and firmware development for VxWorks RTOS. Castellon holds an MSc. and BSc. in Electrical Engineering from the University of Alberta, obtained in 2005 and 1998, respectively.