Shahid Kagathara

Shahid Kagathara is a Senior Staff Physical Design Engineer at NUVIA Inc since May 2021, with previous experience as an ASIC Physical Design Engineer at Cadence Design Systems and Synopsys Inc. Prior roles include Lead Physical Design Engineer at Aricent and Senior Design Engineer at Mirafra Technologies. Shahid has a strong background in the physical design process, handling block ownership from RTL to GDSII and performing tasks such as floorplanning, placement, and timing analysis. Earlier experience includes a role as a CPU Design Co-Op at AMD and an Associate IT consultant at San Jose State University. Shahid holds a Master of Science in Electrical Engineering (VLSI Design) from San Jose State University and a Bachelor of Science in Electronics & Communication from Saurashtra University.