Aravind Jayachandran

Aravind Jayachandran is a Senior ASIC Design Engineer at NVIDIA, where they have been engaged since 2016 in clocks design and timing closure for clock macros. Prior to NVIDIA, Aravind worked at Qualcomm from 2012 to 2014, contributing to RTL integration and mentoring junior engineers, and began their career in FPGA design at C DOT Alcatel Lucent Research Centre in 2011. Aravind earned a Bachelor of Technology in Electronics and Communication Engineering from the National Institute of Technology, Tiruchirappalli, in 2011.