Loana Vo

Loana Vo is currently a Senior ASIC Digital Design Engineer at Synopsys, specializing in ASIC digital design, particularly in high-speed SerDes circuits and innovative solutions for complex challenges. With proficiency in SystemVerilog and extensive hands-on experience in the complete ASIC design flow, Loana has worked on RTL simulation, gate-level simulation, and timing analysis. Previous roles include an intern position at Synopsys, where they contributed to RTL design and testchip tape-outs, as well as stints at Metso and Outotec, providing technical support and engineering assistance, respectively. Loana is pursuing a Bachelor of Engineering in Electrical Engineering at McMaster University, expected to graduate in 2024.