Kavit Patadia

Kavit Patadia is a Senior Physical Design Engineer at Nvidia, bringing over 12 years of experience in physical design implementation and methodology. Kavit has led CPU L2 cache development for subsystem feasibility and convergence and has worked with advanced technologies like TSMC 3nm and Samsung 3gap. Kavit's expertise includes over 11 tape outs and significant contributions to projects involving STA, EMIR, and formal verification, alongside hands-on proficiency with Cadence and Synopsys tools. Previously, Kavit held roles at companies including SiFive, Google, and Qualcomm, enhancing their skills in debugging, mentoring, and cross-site collaboration. Kavit earned a Bachelor of Engineering in Electronic and Communications from Gujarat Technological University.