Mark Villalpando

Mark Villalpando is a Senior ASIC Verification Engineer at NVIDIA, where they are involved in GPU IP design and verification since 2021. Previously, they worked at AMD as an ASIC Design Verification Engineer, focusing on graphics IP and RISC5 command processors from 2019. Prior roles include serving as an ASIC/FPGA Design & Verification Engineer at Lockheed Martin, where they contributed to advanced threat warning systems and targeting sight systems from 2016 to 2019, and as an ASIC/FPGA Engineer at General Dynamics Advanced Information Systems, specializing in satellite payloads from 2012 to 2016. Mark earned a Master of Science in Electrical and Computer Engineering and a Bachelor of Science in Electrical Engineering from the University of Florida between 2007 and 2012.