Sachin Jain

Sachin Jain is a Senior ASIC Design Engineer at NVIDIA, with over eight years of experience in the synthesis and static timing analysis domain. They have expertise in full chip and block synthesis across various technology nodes, including 14nm to 180nm, and have successfully contributed to timing closure on multiple projects. Previously, Sachin worked at notable companies such as Intel Corporation, Broadcom Limited, and AMD, focusing on timing analysis, constraints development, and verification. They earned a Bachelor's degree in Electrical, Electronics, and Communications Engineering from Maulana Azad National Institute of Technology in 2011.