Jay V. is a Design Engineer at NXP Semiconductors since July 2018, with prior experience as a Design and DFT Engineer Intern at Ambarella Inc, where responsibilities included scan insertion, automated STA flow using Python and TCL, and script writing for SDC auto-generation. Jay also served as a grader at Arizona State University for multiple engineering courses, and completed an internship at STMicroelectronics focused on system modeling and architectural development of physical layers. Jay holds a Master of Science in Electrical Engineering from Arizona State University with a perfect GPA and a Bachelor of Technology in Electronics and Communications Engineering from NIRMA University.
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