Eric Gu

Eric Gu is an experienced hardware engineer with a career spanning over two decades in the semiconductor and technology industries. Currently employed at Palo Alto Networks since December 2013, Eric specializes in ASIC verification. Prior to this role, Eric served as a Senior Staff Design Verification Engineer at Samsung Semiconductor Inc, focusing on ARM-based SOC design verification using UVM/OVM and System Verilog. At PLX Technology, Eric was a Verification Lead and contributed to PCI-Express switch/bridge product lines, utilizing RVM/VMM methodologies and Object-Oriented Programming. Eric began the career as a Senior Software Engineer at Teradyne, where skills in C/C++ were applied to develop drivers and diagnostic algorithms for semiconductor test equipment. Eric holds degrees from the University of Arizona, Zhejiang University, and completed secondary education at Hangzhou High School.