Tom Burton

Tom Burton has extensive experience in the field of digital ASIC and FPGA design, with a focus on microarchitecture, specification development, RTL design, verification, and post silicon bring-up and debug. Tom has worked in various roles at companies such as Parade Technologies, Inc., Fresco Logic, Brocade, Sanera Systems, Intel, Altera, and American Microsystems, Inc. Tom has held positions such as Senior Director of Product Development, VP of Engineering, Senior ASIC Engineer, Design Engineer, and Field Application Engineer. Throughout their career, they have gained expertise in Ethernet, PCIe, and Fibre Channel protocols, as well as high-speed datapath and asynchronous logic.

Tom Burton attended Minnesota State University, Mankato from 1982 to 1986 and earned a Bachelor of Science degree in Electrical Engineering Technology.